/**
  ******************************************************************************
  * @file    mtu.h
  * @author  hyseim software Team
  * @date    02-Aug-2023
  * @brief   This file provides all the headers of the mtu functions.
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2020 Hyseim. Co., Ltd.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MTU_H__
#define __MTU_H__
/* Includes ------------------------------------------------------------------*/
#include "chip_define.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

#define ICLK_1              0x0
#define ICLK_4              0x1
#define ICLK_16             0x2
#define ICLK_64             0x3
#define MTCLKA              0x4
#define MTCLKB              0x5
#define MTCLKC              0X6
#define MTCLKD              0X7
#define Mtu1_Mtu2_cnt       0x7
#define Mtu2_ICLK_1024      0x7
#define Mtu3467_ICLK_256    0x4
#define Mtu3467_ICLK_1024   0x5
#define Mtu3467_MTCLKA      0x6
#define Mtu3467_MTCLKB      0x7
#define Rising_edge         0x0
#define Falling_edge        0x1
#define Bilateral_edge      0x2
#define No_clear            0x0
#define TGRA_Input          0x1
#define TGRB_Input          0x2
#define Sync_clear          0x3
#define Mtu03467_No_clear   0x4
#define TGRC_Input          0x5
#define TGRD_Input          0x6
// #define Mtu03467_No_clear   0x7
#define High_level          0x1
#define Low_level           0x0
#define Enable              0x1
#define Disable             0x0
#define Inital_low_com_low  0x1
#define Inital_low_com_high 0x2
#define Inital_low_com_alte 0x3
#define Inital_high_com_low 0x5
#define Inital_high_com_hig 0x6
#define Inital_high_com_alt 0x7
#define Ope_mode_phr_set    0x1
#define Pwm_mode_1          0x2
#define Pwm_mode_2          0x3
#define Phase_mode_1        0x4
#define Phase_mode_2        0x5
#define Phase_mode_3        0x6
#define Phase_mode_4        0x7
#define Reset_syn_pwm_mode  0x8
#define Cannot_set          0x9
#define Comple_pwm_mode_1   0xd
#define Comple_pwm_mode_2   0xe
#define Comple_pwm_mode_3   0xf

#define MTU0_TCR        MTU0_BASE + 0x300
#define MTU0_TMDR1      MTU0_BASE + 0x301
#define MTU0_TIORH      MTU0_BASE + 0x302
#define MTU0_TIORL      MTU0_BASE + 0x303
#define MTU0_TIER       MTU0_BASE + 0x304
#define MTU0_TSR        MTU0_BASE + 0x305
#define MTU0_TCNT       MTU0_BASE + 0x306
#define MTU0_TGRA       MTU0_BASE + 0x308
#define MTU0_TGRB       MTU0_BASE + 0x30a
#define MTU0_TGRC       MTU0_BASE + 0x30c
#define MTU0_TGRD       MTU0_BASE + 0x30e
#define MTU0_TGRE       MTU0_BASE + 0x320
#define MTU0_TGRF       MTU0_BASE + 0x322
#define MTU0_TIER2      MTU0_BASE + 0x324
#define MTU0_TSR2       MTU0_BASE + 0x325
#define MTU0_TBTM       MTU0_BASE + 0x326

#define MTU1_TCR        MTU0_BASE + 0x380
#define MTU1_TMDR1      MTU0_BASE + 0x381
#define MTU1_TIOR       MTU0_BASE + 0x382
#define MTU1_TIER       MTU0_BASE + 0x384
#define MTU1_TSR        MTU0_BASE + 0x385
#define MTU1_TCNT       MTU0_BASE + 0x386
#define MTU1_TGRA       MTU0_BASE + 0x388
#define MTU1_TGRB       MTU0_BASE + 0x38a
#define MTU1_TICCR      MTU0_BASE + 0x390

#define MTU2_TCR        MTU0_BASE + 0x400
#define MTU2_TMDR1      MTU0_BASE + 0x401
#define MTU2_TIOR       MTU0_BASE + 0x402
#define MTU2_TIER       MTU0_BASE + 0x404
#define MTU2_TSR        MTU0_BASE + 0x405
#define MTU2_TCNT       MTU0_BASE + 0x406
#define MTU2_TGRA       MTU0_BASE + 0x408
#define MTU2_TGRB       MTU0_BASE + 0x40a

#define MTU3_TCR        MTU0_BASE + 0x200
#define MTU3_TMDR1      MTU0_BASE + 0x202
#define MTU3_TIORH      MTU0_BASE + 0x204
#define MTU3_TIORL      MTU0_BASE + 0x205
#define MTU3_TIER       MTU0_BASE + 0x208
#define MTU3_TCNT       MTU0_BASE + 0x210
#define MTU3_TGRA       MTU0_BASE + 0x218
#define MTU3_TGRB       MTU0_BASE + 0x21a
#define MTU3_TGRC       MTU0_BASE + 0x224
#define MTU3_TGRD       MTU0_BASE + 0x226
#define MTU3_TGRE       MTU0_BASE + 0x272
#define MTU3_TSR        MTU0_BASE + 0x22c
#define MTU3_TBTM       MTU0_BASE + 0x238

#define MTU4_TCR        MTU0_BASE + 0x201
#define MTU4_TMDR1      MTU0_BASE + 0x203
#define MTU4_TIORH      MTU0_BASE + 0x206
#define MTU4_TIORL      MTU0_BASE + 0x207
#define MTU4_TIER       MTU0_BASE + 0x209
#define MTU4_TCNT       MTU0_BASE + 0x212
#define MTU4_TGRA       MTU0_BASE + 0x21c
#define MTU4_TGRB       MTU0_BASE + 0x21e
#define MTU4_TGRC       MTU0_BASE + 0x228
#define MTU4_TGRD       MTU0_BASE + 0x22a
#define MTU4_TGRE       MTU0_BASE + 0x274
#define MTU4_TGRF       MTU0_BASE + 0x276
#define MTU4_TSR        MTU0_BASE + 0x22d
#define MTU4_TBTM       MTU0_BASE + 0x239
#define MTU4_TADCR      MTU0_BASE + 0x240
#define MTU4_TADCORA    MTU0_BASE + 0x244
#define MTU4_TADCORB    MTU0_BASE + 0x246
#define MTU4_TADCOBRA   MTU0_BASE + 0x248
#define MTU4_TADCOBRB   MTU0_BASE + 0x24a

#define MTU5_TCNTU      MTU0_BASE + 0xc80
#define MTU5_TGRU       MTU0_BASE + 0xc82
#define MTU5_TCRU       MTU0_BASE + 0xc84
#define MTU5_TIORU      MTU0_BASE + 0xc86
#define MTU5_TCNTV      MTU0_BASE + 0xc90
#define MTU5_TGRV       MTU0_BASE + 0xc92
#define MTU5_TCRV       MTU0_BASE + 0xc94
#define MTU5_TIORV      MTU0_BASE + 0xc96
#define MTU5_TCNTW      MTU0_BASE + 0xca0
#define MTU5_TGRW       MTU0_BASE + 0xca2
#define MTU5_TCRW       MTU0_BASE + 0xca4
#define MTU5_TIORW      MTU0_BASE + 0xca6
#define MTU5_TSR        MTU0_BASE + 0xcb0
#define MTU5_TIER       MTU0_BASE + 0xcb2
#define MTU5_TSTR       MTU0_BASE + 0xcb4
#define MTU5_TCNTCMPCLR MTU0_BASE + 0xcb6

#define MTU6_TCR        MTU0_BASE + 0xa00
#define MTU6_TMDR1      MTU0_BASE + 0xa02
#define MTU6_TIORH      MTU0_BASE + 0xa04
#define MTU6_TIORL      MTU0_BASE + 0xa05
#define MTU6_TIER       MTU0_BASE + 0xa08
#define MTU6_TCNT       MTU0_BASE + 0xa10
#define MTU6_TGRA       MTU0_BASE + 0xa18
#define MTU6_TGRB       MTU0_BASE + 0xa1a
#define MTU6_TGRC       MTU0_BASE + 0xa24
#define MTU6_TGRD       MTU0_BASE + 0xa26
#define MTU6_TGRE       MTU0_BASE + 0xa72
#define MTU6_TSYCR      MTU0_BASE + 0xa50
#define MTU6_TSR        MTU0_BASE + 0xa2c
#define MTU6_TBTM       MTU0_BASE + 0xa38

#define MTU7_TCR        MTU0_BASE + 0xa01
#define MTU7_TMDR1      MTU0_BASE + 0xa03
#define MTU7_TIORH      MTU0_BASE + 0xa06
#define MTU7_TIORL      MTU0_BASE + 0xa07
#define MTU7_TIER       MTU0_BASE + 0xa09
#define MTU7_TCNT       MTU0_BASE + 0xa12
#define MTU7_TGRA       MTU0_BASE + 0xa1c
#define MTU7_TGRB       MTU0_BASE + 0xa1e
#define MTU7_TGRC       MTU0_BASE + 0xa28
#define MTU7_TGRD       MTU0_BASE + 0xa2a
#define MTU7_TGRE       MTU0_BASE + 0xa74
#define MTU7_TGRF       MTU0_BASE + 0xa76
#define MTU7_TSR        MTU0_BASE + 0xa2d
#define MTU7_TBTM       MTU0_BASE + 0xa39
#define MTU7_TADCR      MTU0_BASE + 0xa40
#define MTU7_TADCORA    MTU0_BASE + 0xa44
#define MTU7_TADCORB    MTU0_BASE + 0xa46
#define MTU7_TADCOBRA   MTU0_BASE + 0xa48
#define MTU7_TADCOBRB   MTU0_BASE + 0xa4a

#define MTU_TOERA       MTU0_BASE + 0x20a
#define MTU_TOERB       MTU0_BASE + 0xa0a
#define MTU_TGCRA       MTU0_BASE + 0x20d
#define MTU_TOCR1A      MTU0_BASE + 0x20e
#define MTU_TOCR1B      MTU0_BASE + 0xa0e
#define MTU_TOCR2A      MTU0_BASE + 0x20f
#define MTU_TOCR2B      MTU0_BASE + 0xa0f
#define MTU_TCDRA       MTU0_BASE + 0x214
#define MTU_TCDRB       MTU0_BASE + 0xa14
#define MTU_TDDRA       MTU0_BASE + 0x216
#define MTU_TDERA       MTU0_BASE + 0x234
#define MTU_TDDRB       MTU0_BASE + 0xa16
#define MTU_TDERB       MTU0_BASE + 0xa34
#define MTU_TCNTSA      MTU0_BASE + 0x220
#define MTU_TCNTSB      MTU0_BASE + 0xa20
#define MTU_TCBRA       MTU0_BASE + 0x222
#define MTU_TCBRB       MTU0_BASE + 0xa22
#define MTU_TITCR1A     MTU0_BASE + 0x230
#define MTU_TITCR1B     MTU0_BASE + 0xa30
#define MTU_TITCR2A     MTU0_BASE + 0x23b
#define MTU_TITCR2B     MTU0_BASE + 0xa3b
#define MTU_TITCNT1A    MTU0_BASE + 0x231
#define MTU_TITCNT1B    MTU0_BASE + 0xa31
#define MTU_TITCNT2A    MTU0_BASE + 0x23c
#define MTU_TITCNT2B    MTU0_BASE + 0xa3c
#define MTU_TBTERA      MTU0_BASE + 0x232
#define MTU_TBTERB      MTU0_BASE + 0xa32
#define MTU_TOLBRA      MTU0_BASE + 0x236
#define MTU_TOLBRB      MTU0_BASE + 0xa36
#define MTU_TMDR2A      MTU0_BASE + 0x270
#define MTU_TMDR2B      MTU0_BASE + 0xa70
#define MTU_TITMRA      MTU0_BASE + 0x23a
#define MTU_TITMRB      MTU0_BASE + 0xa3a
#define MTU_TWCRA       MTU0_BASE + 0x260
#define MTU_TWCRB       MTU0_BASE + 0xa60
#define MTU_TSTRA       MTU0_BASE + 0x280
#define MTU_TSTRB       MTU0_BASE + 0xa80
#define MTU_TSYRA       MTU0_BASE + 0x281
#define MTU_TSYRB       MTU0_BASE + 0xa81
#define MTU_TCSYSTR     MTU0_BASE + 0x282
#define MTU_TRWERA      MTU0_BASE + 0x284
#define MTU_TRWERB      MTU0_BASE + 0xa84
#define MTU_MSIC        MTU0_BASE + 0xcfc


//MTU1
#define MTU1_0_TCR        MTU1_BASE + 0x300
#define MTU1_0_TMDR1      MTU1_BASE + 0x301
#define MTU1_0_TIORH      MTU1_BASE + 0x302
#define MTU1_0_TIORL      MTU1_BASE + 0x303
#define MTU1_0_TIER       MTU1_BASE + 0x304
#define MTU1_0_TSR        MTU1_BASE + 0x305
#define MTU1_0_TCNT       MTU1_BASE + 0x306
#define MTU1_0_TGRA       MTU1_BASE + 0x308
#define MTU1_0_TGRB       MTU1_BASE + 0x30a
#define MTU1_0_TGRC       MTU1_BASE + 0x30c
#define MTU1_0_TGRD       MTU1_BASE + 0x30e
#define MTU1_0_TGRE       MTU1_BASE + 0x320
#define MTU1_0_TGRF       MTU1_BASE + 0x322
#define MTU1_0_TIER2      MTU1_BASE + 0x324
#define MTU1_0_TSR2       MTU1_BASE + 0x325
#define MTU1_0_TBTM       MTU1_BASE + 0x326

#define MTU1_1_TCR        MTU1_BASE + 0x380
#define MTU1_1_TMDR1      MTU1_BASE + 0x381
#define MTU1_1_TIOR       MTU1_BASE + 0x382
#define MTU1_1_TIER       MTU1_BASE + 0x384
#define MTU1_1_TSR        MTU1_BASE + 0x385
#define MTU1_1_TCNT       MTU1_BASE + 0x386
#define MTU1_1_TGRA       MTU1_BASE + 0x388
#define MTU1_1_TGRB       MTU1_BASE + 0x38a
#define MTU1_1_TICCR      MTU1_BASE + 0x390

#define MTU1_2_TCR        MTU1_BASE + 0x400
#define MTU1_2_TMDR1      MTU1_BASE + 0x401
#define MTU1_2_TIOR       MTU1_BASE + 0x402
#define MTU1_2_TIER       MTU1_BASE + 0x404
#define MTU1_2_TSR        MTU1_BASE + 0x405
#define MTU1_2_TCNT       MTU1_BASE + 0x406
#define MTU1_2_TGRA       MTU1_BASE + 0x408
#define MTU1_2_TGRB       MTU1_BASE + 0x40a

#define MTU1_3_TCR        MTU1_BASE + 0x200
#define MTU1_3_TMDR1      MTU1_BASE + 0x202
#define MTU1_3_TIORH      MTU1_BASE + 0x204
#define MTU1_3_TIORL      MTU1_BASE + 0x205
#define MTU1_3_TIER       MTU1_BASE + 0x208
#define MTU1_3_TCNT       MTU1_BASE + 0x210
#define MTU1_3_TGRA       MTU1_BASE + 0x218
#define MTU1_3_TGRB       MTU1_BASE + 0x21a
#define MTU1_3_TGRC       MTU1_BASE + 0x224
#define MTU1_3_TGRD       MTU1_BASE + 0x226
#define MTU1_3_TGRE       MTU1_BASE + 0x272
#define MTU1_3_TSR        MTU1_BASE + 0x22c
#define MTU1_3_TBTM       MTU1_BASE + 0x238

#define MTU1_4_TCR        MTU1_BASE + 0x201
#define MTU1_4_TMDR1      MTU1_BASE + 0x203
#define MTU1_4_TIORH      MTU1_BASE + 0x206
#define MTU1_4_TIORL      MTU1_BASE + 0x207
#define MTU1_4_TIER       MTU1_BASE + 0x209
#define MTU1_4_TCNT       MTU1_BASE + 0x212
#define MTU1_4_TGRA       MTU1_BASE + 0x21c
#define MTU1_4_TGRB       MTU1_BASE + 0x21e
#define MTU1_4_TGRC       MTU1_BASE + 0x228
#define MTU1_4_TGRD       MTU1_BASE + 0x22a
#define MTU1_4_TGRE       MTU1_BASE + 0x274
#define MTU1_4_TGRF       MTU1_BASE + 0x276
#define MTU1_4_TSR        MTU1_BASE + 0x22d
#define MTU1_4_TBTM       MTU1_BASE + 0x239
#define MTU1_4_TADCR      MTU1_BASE + 0x240
#define MTU1_4_TADCORA    MTU1_BASE + 0x244
#define MTU1_4_TADCORB    MTU1_BASE + 0x246
#define MTU1_4_TADCOBRA   MTU1_BASE + 0x248
#define MTU1_4_TADCOBRB   MTU1_BASE + 0x24a

#define MTU1_5_TCNTU      MTU1_BASE + 0xc80
#define MTU1_5_TGRU       MTU1_BASE + 0xc82
#define MTU1_5_TCRU       MTU1_BASE + 0xc84
#define MTU1_5_TIORU      MTU1_BASE + 0xc86
#define MTU1_5_TCNTV      MTU1_BASE + 0xc90
#define MTU1_5_TGRV       MTU1_BASE + 0xc92
#define MTU1_5_TCRV       MTU1_BASE + 0xc94
#define MTU1_5_TIORV      MTU1_BASE + 0xc96
#define MTU1_5_TCNTW      MTU1_BASE + 0xca0
#define MTU1_5_TGRW       MTU1_BASE + 0xca2
#define MTU1_5_TCRW       MTU1_BASE + 0xca4
#define MTU1_5_TIORW      MTU1_BASE + 0xca6
#define MTU1_5_TSR        MTU1_BASE + 0xcb0
#define MTU1_5_TIER       MTU1_BASE + 0xcb2
#define MTU1_5_TSTR       MTU1_BASE + 0xcb4
#define MTU1_5_TCNTCMPCLR MTU1_BASE + 0xcb6

#define MTU1_6_TCR        MTU1_BASE + 0xa00
#define MTU1_6_TMDR1      MTU1_BASE + 0xa02
#define MTU1_6_TIORH      MTU1_BASE + 0xa04
#define MTU1_6_TIORL      MTU1_BASE + 0xa05
#define MTU1_6_TIER       MTU1_BASE + 0xa08
#define MTU1_6_TCNT       MTU1_BASE + 0xa10
#define MTU1_6_TGRA       MTU1_BASE + 0xa18
#define MTU1_6_TGRB       MTU1_BASE + 0xa1a
#define MTU1_6_TGRC       MTU1_BASE + 0xa24
#define MTU1_6_TGRD       MTU1_BASE + 0xa26
#define MTU1_6_TGRE       MTU1_BASE + 0xa72
#define MTU1_6_TSYCR      MTU1_BASE + 0xa50
#define MTU1_6_TSR        MTU1_BASE + 0xa2c
#define MTU1_6_TBTM       MTU1_BASE + 0xa38

#define MTU1_7_TCR        MTU1_BASE + 0xa01
#define MTU1_7_TMDR1      MTU1_BASE + 0xa03
#define MTU1_7_TIORH      MTU1_BASE + 0xa06
#define MTU1_7_TIORL      MTU1_BASE + 0xa07
#define MTU1_7_TIER       MTU1_BASE + 0xa09
#define MTU1_7_TCNT       MTU1_BASE + 0xa12
#define MTU1_7_TGRA       MTU1_BASE + 0xa1c
#define MTU1_7_TGRB       MTU1_BASE + 0xa1e
#define MTU1_7_TGRC       MTU1_BASE + 0xa28
#define MTU1_7_TGRD       MTU1_BASE + 0xa2a
#define MTU1_7_TGRE       MTU1_BASE + 0xa74
#define MTU1_7_TGRF       MTU1_BASE + 0xa76
#define MTU1_7_TSR        MTU1_BASE + 0xa2d
#define MTU1_7_TBTM       MTU1_BASE + 0xa39
#define MTU1_7_TADCR      MTU1_BASE + 0xa40
#define MTU1_7_TADCORA    MTU1_BASE + 0xa44
#define MTU1_7_TADCORB    MTU1_BASE + 0xa46
#define MTU1_7_TADCOBRA   MTU1_BASE + 0xa48
#define MTU1_7_TADCOBRB   MTU1_BASE + 0xa4a

#define MTU1_TOERA       MTU1_BASE + 0x20a
#define MTU1_TOERB       MTU1_BASE + 0xa0a
#define MTU1_TGCRA       MTU1_BASE + 0x20d
#define MTU1_TOCR1A      MTU1_BASE + 0x20e
#define MTU1_TOCR1B      MTU1_BASE + 0xa0e
#define MTU1_TOCR2A      MTU1_BASE + 0x20f
#define MTU1_TOCR2B      MTU1_BASE + 0xa0f
#define MTU1_TCDRA       MTU1_BASE + 0x214
#define MTU1_TCDRB       MTU1_BASE + 0xa14
#define MTU1_TDDRA       MTU1_BASE + 0x216
#define MTU1_TDERA       MTU1_BASE + 0x234
#define MTU1_TDDRB       MTU1_BASE + 0xa16
#define MTU1_TDERB       MTU1_BASE + 0xa34
#define MTU1_TCNTSA      MTU1_BASE + 0x220
#define MTU1_TCNTSB      MTU1_BASE + 0xa20
#define MTU1_TCBRA       MTU1_BASE + 0x222
#define MTU1_TCBRB       MTU1_BASE + 0xa22
#define MTU1_TITCR1A     MTU1_BASE + 0x230
#define MTU1_TITCR1B     MTU1_BASE + 0xa30
#define MTU1_TITCR2A     MTU1_BASE + 0x23b
#define MTU1_TITCR2B     MTU1_BASE + 0xa3b
#define MTU1_TITCNT1A    MTU1_BASE + 0x231
#define MTU1_TITCNT1B    MTU1_BASE + 0xa31
#define MTU1_TITCNT2A    MTU1_BASE + 0x23c
#define MTU1_TITCNT2B    MTU1_BASE + 0xa3c
#define MTU1_TBTERA      MTU1_BASE + 0x232
#define MTU1_TBTERB      MTU1_BASE + 0xa32
#define MTU1_TOLBRA      MTU1_BASE + 0x236
#define MTU1_TOLBRB      MTU1_BASE + 0xa36
#define MTU1_TMDR2A      MTU1_BASE + 0x270
#define MTU1_TMDR2B      MTU1_BASE + 0xa70
#define MTU1_TITMRA      MTU1_BASE + 0x23a
#define MTU1_TITMRB      MTU1_BASE + 0xa3a
#define MTU1_TWCRA       MTU1_BASE + 0x260
#define MTU1_TWCRB       MTU1_BASE + 0xa60
#define MTU1_TSTRA       MTU1_BASE + 0x280
#define MTU1_TSTRB       MTU1_BASE + 0xa80
#define MTU1_TSYRA       MTU1_BASE + 0x281
#define MTU1_TSYRB       MTU1_BASE + 0xa81
#define MTU1_TCSYSTR     MTU1_BASE + 0x282
#define MTU1_TRWERA      MTU1_BASE + 0x284
#define MTU1_TRWERB      MTU1_BASE + 0xa84

/* Exported macro ------------------------------------------------------------*/
#define get_field(x,m,n)        (x & (((~0U)>>(31-(m-n)))<<(n))) >> (n)
#define set_field(x,y,m,n)      (x & (~(((~0U)>>(31-(m-n)))<<(n)))) | (y <<(n))
#define reg16       *(unsigned short volatile *)
#define reg8        *(unsigned char volatile *)
/* Exported functions ------------------------------------------------------- */

extern volatile unsigned int irq_triggered;
extern volatile unsigned int count_state;

extern void  __attribute__ ((interrupt)) mtu0_tgiv7_handler(void);
extern void  __attribute__ ((interrupt)) mtu1_tgiv7_handler(void);
extern void mtu67_pad_init(void);
extern void mtu671_pad_init(void);
#endif
